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| 1996 the m pd17107(a1) is a tiny microcontroller consisting of 1k-byte (512 16 bits) rom, 16 4 bit ram, and 11 input/output ports. the 17k architecture, which uses general registers to directly manipulate data memory, is employed for effective programming. every instruction is 1 word long, consisting of 16 bits. features ? program memory (rom) : 1k bytes (512 16 bits) ? data memory (ram) : 16 4 bits ? input/output ports : 11 ports (including three n-ch open-drain outputs) ? instruction execution time : 128 m s (at f cc = 62.5 khz) to 8 m s (at f cc = 1 mhz) ? stack level : 1 ? a standby function (with the halt and stop modes) note the capacitor for rc oscillator is contained in the m pd17107(a1). applications electronic units for automobiles, and suchlike ordering information part number package quality grade m pd17107cx(a1)- 16-pin plastic dip (300 mil) special m pd17107gs(a1)- 16-pin plastic sop (300 mil) special remark : rom code number the information in this document is subject to change without notice. data sheet mos integrated circuit 4 bit single-chip microcontroller m pd17107(a1) ? data memory can retain data on low voltage (2.0 v at minimum). ? an rc oscillator note for the system clock: with a built-in capacitor (only a resistor is required to be connected.) ? supply voltage: v dd = 2.5 to 6.0 v (at f cc = 250 khz) v dd = 4.5 to 6.0 v (at f cc = 1 mhz) ? operating ambient temperature: t a = C40 to +110 ?c document no. u10915ej1v0ds00 (1st edition) date published january 1996 p printed in japan please refer to "quality grade on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. each device has a different capacity of a built-in capacitor for system clock oscillation of the m pd17107(a1). this causes the frequency deviation within about 30% even though the connected resistors have the same value. use the m pd17103(a1) (ceramic based oscillation) when the deviation is a critical problem.
2 m pd17107(a1) functions pin configuration (top view) 16-pin plastic dip 16-pin plastic sop 1k byte (512 16 bits) 16 4 bits 1 level 11 (n-ch open-drain output ports: 3) rc oscillation 128 m s (f cc = 62.5 khz) to 8 m s (f cc = 1 mhz) halt/stop 2.5 to 6.0 v (at f cc = 62.5 khz to 250 khz) 4.5 to 6.0 v (at f cc = 62.5 khz to 1 mhz) 16-pin plastic dip (300 mil) 16-pin plastic sop (300 mil) m pd17p107 the quality grade is "standard," not "a1." operating ambient temperature: t a = C40 to +85 c item function 1 2 3 4 5 6 7 8 osc 1 osc 0 reset p0d 0 p0d 1 p0d 2 p0d 3 v dd 16 15 14 13 12 11 10 9 pd17107cx (a1)- ?? pd17107gs (a1)- ?? gnd p0b 2 p0b 1 /rls stop p0b 0 /rls halt p0c 3 p0c 2 p0c 1 p0c 0 m m caution although a prom product is highly compatible with a masked rom product in respect of functions, they differ in internal rom circuits and part of electrical characteristics. before changing the prom product to the masked rom product in an application system, evaluate the system carefully using the masked rom product. rom ram stack number of i/o ports system clock (f cc ) instruction execution time standby function operating supply voltage package one-time prom 3 m pd17107(a1) block diagram cpu clk clk stop alu n-ch open drain p0d cmos p0c cmos p0b 0 /rls halt p0b 1 /rls stop p0b 2 p0c 0 p0c 1 p0c 2 p0c 3 p0d 0 p0d 1 p0d 2 p0d 3 v dd gnd reset instruc- tion decoder program counter osc 0 osc 1 p0b stack1 9 bits rom 512 16 bits system clock generator ram 16 4 bits 4 m pd17107(a1) pin functions pin functions ? port pins ? non-port pins i/o: input/output p0b 0 /rls halt p0b 1 /rls stop p0b 2 p0c 0 -p0c 3 p0d 0 -p0d 3 i/o i/o i/o for releasing the halt mode for releasing the stop mode ? n-ch open-drain 3-bit i/o port (port 0b) ? a built-in pull-up resistor can be connected with a mask option bit by bit. ? this open-drain port has a withstand voltage of 9 v. cmos (push-pull) 4-bit i/o port (port 0c) cmos (push-pull) 4-bit i/o port (port 0d) ? open-drain: high impedance (input mode) ? with pull-up resistor selected: high level (input mode) high impedance (input mode) high impedance (input mode) pin i/o reset input C C C pin i/o function ? reset input pin ? a built-in pull-up resistor can be connected with a mask option. positive power supply pin gnd pin pins to be connected to the resistor for system clock oscillation reset v dd gnd osc 0 , osc 1 function 5 m pd17107(a1) equivalent input/output circuits below are simplified diagrams of the equivalent input/output circuits. (1) p0c and p0d (2) p0b 0 and p0b 1 dd v in / out p-ch n-ch p-ch n-ch dd v data output disable dd v in / out pull-up resistor (mask option) n-ch data output disable dd v p-ch n-ch stand-by release 6 m pd17107(a1) (3) p0b 2 (4) reset dd v in / out pull-up resistor (mask option) n-ch data output disable dd v p-ch n-ch pull-up resistor (mask option) dd v in 7 m pd17107(a1) handling unused pins when connecting unused pins, the following conditions and handling are recommended: note when a pin is pulled up (connected to v dd through a resistor) or pulled down (connected to ground through a resistor) outside the chip, take the driving capacity and maximum current consumption of a port into consideration. when using high-resistance pull-up or pull-down resistors, apply appropriate countermeas- ures to ensure that noise is not attracted by the resistors. although the optimum pull-up or pull-down resistor varies with the application circuit, in general a resistor of 10 to 100 kilohms is suitable. caution to fix the output level of a pin, it is recommended that the level be specified repeatedly within a loop in a program. notes on use of the reset pin the reset pin has the test mode selecting function for testing the internal operation of the m pd17107(a1) (ic test), besides the functions shown in " pin functions ." applying a voltage exceeding v dd to the reset pin causes the m pd17107(a1) to enter the test mode. when noise exceeding v dd comes in during normal operation, the device is switched to the test mode. for example, if the wiring from the reset pin is too long, noise may be induced on the wiring, causing this mode switching. when installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. if noise yet arises, use an external part to suppress it as shown below. ? connect a diode with low v f between the pin ? connect a capacitor between the pin and v dd . and v dd . pin recommended conditions and handling internal external port input mode output mode p0c, p0d p0b p0c, p0d (cmos port) p0b (n-ch open- drain port) connect each pin to v dd or to ground through a resistor note . leave open. pull-up resistors that can be specified by the mask option are not incorporated. pull-up resistors that can be specified with the mask option are incorporated. outputs low level without pull-up resistors that can be specified with the mask option. outputs high level with pull-up resistors that can be specified with the mask option. v dd reset v dd diode with low v f v dd reset v dd 8 m pd17107(a1) contents 1. program counter (pc) ...................................................................................................... 10 1.1 configuration of the program counter (pc) ............................................................ 10 1.2 functions of the program counter (pc) ..................................................................... 10 2. stack ............................................................................................................................... .......... 11 3. program memory (rom) ..................................................................................................... 12 4. data memory (ram) .............................................................................................................. 13 4.1 configuration of the data memory (ram) ................................................................... 13 4.1.1 functions of the general data memory ...................................................................... 13 4.1.2 functions of the general register .............................................................................. 13 4.1.3 functions of the port register .................................................................................... 13 4.1.4 functions of the system register ............................................................................... 14 5. alu block ............................................................................................................................... .17 5.1 alu block configuration .................................................................................................... 17 5.2 functions of the alu block ............................................................................................... 17 5.2.1 functions of the alu .................................................................................................... 17 5.2.2 functions of temporary registers a and b .............................................................. 22 5.2.3 functions of the status flip-flop ................................................................................ 22 5.2.4 performing operations in 4-bit binary ....................................................................... 23 5.2.5 performing operations in bcd .................................................................................... 23 5.2.6 performing operations in the alu block .................................................................. 24 5.3 arithmetic operations (addition and subtraction in 4-bit binary and bcd) . 25 5.3.1 addition and subtraction when cmp = 0 and bcd = 0 ........................................... 25 5.3.2 addition and subtraction when cmp = 1 and bcd = 0 ........................................... 25 5.3.3 addition and subtraction when cmp = 0 and bcd = 1 ........................................... 26 5.3.4 addition and subtraction when cmp = 1 and bcd = 1 ........................................... 26 5.3.5 warnings concerning use of arithmetic operations ............................................... 27 5.4 logical operations ................................................................................................................ 27 5.5 bit evaluations ........................................................................................................................ 28 5.5.1 true (1) bit evaluation ................................................................................................ 28 5.5.2 false (0) bit evaluation .............................................................................................. 29 5.6 comparison evaluations ..................................................................................................... 29 5.6.1 "equal" evaluation ........................................................................................................ 30 5.6.2 "not equal" evaluation ................................................................................................. 30 5.6.3 "greater than or equal" evaluation ........................................................................... 31 5.6.4 "less than" evaluation ................................................................................................ 31 5.7 rotations ............................................................................................................................... ..... 32 5.7.1 rotation to the right ..................................................................................................... 32 5.7.2 rotation to the left ........................................................................................................ 33 9 m pd17107(a1) 6. ports ............................................................................................................................... .......... 34 6.1 port 0b (p0b 0 /rls halt , p0b 1 /rls stop , p0b 2 ) .......................................................................... 34 6.2 port 0c (p0c 0 to p0c 3 ) .............................................................................................................. 34 6.3 port 0d (p0d 0 to p0d 3 ) .............................................................................................................. 34 6.4 notes on manipulating port registers ....................................................................... 36 7. standby functions ............................................................................................................. 37 7.1 halt mode ............................................................................................................................... ..... 37 7.2 stop mode ............................................................................................................................... ..... 37 7.3 setting and releasing the standby modes ................................................................ 37 7.4 hardware statuses in standby mode ........................................................................... 38 7.5 timing for releasing the standby modes ................................................................... 38 8. reset function ..................................................................................................................... 40 8.1 reset function ......................................................................................................................... 40 9. reserved words used in assembly language ...................................................... 41 9.1 mask-option pseudo instructions .................................................................................. 41 9.1.1 option and endop pseudo instructions ................................................................. 41 9.1.2 mask-option definition pseudo instructions ............................................................ 41 9.2 reserved symbols .................................................................................................................. 43 10. instruction set .................................................................................................................... 44 10.1 instruction set list ............................................................................................................... 44 10.2 instructions .............................................................................................................................. 4 5 10.3 assembler (as17k) built-in macro instructions ....................................................... 47 11. electrical characteristics .......................................................................................... 48 12. characteristic curves (reference) .......................................................................... 52 13. package drawings .............................................................................................................. 54 14. recommended soldering conditions ......................................................................... 58 appendix development tools ............................................................................................. 59 10 m pd17107(a1) 1. program counter (pc) 1.1 configuration of the program counter (pc) as shown in fig. 1-1, the program counter is a 9-bit binary counter. fig. 1-1 program counter 1.2 functions of the program counter (pc) the program counter specifies the address of a program memory (rom) or a program. usually, every time an instruction is executed, the program counter is incremented by one. when a branch instruction (br), a subroutine call instruction (call), or a return instruction (ret) is executed, the address specified in the operand is loaded in the pc. then the instruction in the address is executed. when a skip instruction is executed, the address of the instruction next to the skip instruction is specified irrespective of the contents of the skip instruction. if the skip conditions are satisfied, the instruction next to the skip instruction is regarded as a no operation (nop) instruction. so, the nop instruction is executed and the address of the next instruction is specified. pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 9 bits 11 m pd17107(a1) 2. stack stack of the m pd17107(a1) is a register in which the return address of a program is saved when a subroutine call instruction is executed. one level of address stack is provided. fig. 2-1 shows the relationship between the pc, the stack, and the operand of br and call instructions. fig. 2-1 relationship between the pc, the stack, and the operand of br and call instructions in fig. 2-1, ahn, amn, and aln (0 n 3) indicate bit positions in a 16-bit instruction as follows: fig. 2-2 configuration of a 16-bit instruction when the assembler is not used and a br or call instruction is used, ah2 and ah1 must be set to 0. reset input clears all bits of the program counter to 0. pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 s8 s7 s6 s5 s4 s3 s2 s1 s0 ah0 am3 am2 am1 am0 al3 al2 al1 al0 call br, call ret retsk instructions pc stack operand of br and call instructions msb lsb br and call instructions fh eh dh ch bh ah 9h 8h 7h 6h 5h 4h 3h 2h 1h 0h ah2 ah1 ah0 am3 am2 am1 am0 al3 al2 al1 al0 operation code operand 12 m pd17107(a1) 3. program memory (rom) fig. 3-1 shows the program memory (rom) configuration. as shown in the figure, the program memory has 512 words by 16 bits. the program memory has been addressed in units of 16 bits. the addresses 0000h to 01ffh are specified by the program counter (pc). every instruction is a 1 word long, consisting of 16 bits. one instruction can therefore be stored at one address in program memory. address 0000h is used as a reset start address. fig. 3-1 program memory map 0000h 01ffh 16 bits 512 words 13 m pd17107(a1) 4. data memory (ram) the data memory (ram) stores data of arithmetic/logic and control operations. data can be always written to or read from it by means of instructions. 4.1 configuration of the data memory (ram) fig. 4-1 shows the configuration of the data memory (ram). the data memory is configured in units of four bits, or one nibble, and an address is assigned to each four bits of data. the high-order three bits are called the row address, and the low-order four bits are called the column address. according to its functions, the data memory is divided into three blocks as shown below: general data memory, port register, and system register. fig. 4-1 data memory map 4.1.1 functions of the general data memory the general data memory is a part of the data memory from which the system register (sysreg) and port register are excluded. by executing a data memory manipulation instruction, a four-bit arithmetic operation and comparison, evaluation, and transfer between data on data memory and any immediate data can be executed with a single operation. 4.1.2 functions of the general register the general register indicates any identical row address (16 nibbles) in the data memory specified in the register pointer (rp) in the system register. since the m pd17107(a1) register pointer is always set to 0, the general data memory is also used as a general register. the general register can operate or transfer data to and from the data memory. 4.1.3 functions of the port register the port register is used to set output data or to read the input data of input/output ports. once data is written to the port register corresponding to a port, the port is set to output mode and outputs the data unless another data is rewritten (the output mode is maintained until the port register is reset). whenever a read instruction is executed for a port register, the read data indicates the states of the pins, not the value of the port register , regardless of whether the pins are in the input or output mode. 012 3 45 678 9abc def 0 7 general data memory (general register) port register system register column address row address 14 m pd17107(a1) 4.1.4 functions of the system register the system register controls the cpu. the program status word (psword) is the only system register in the m pd17107(a1). fig. 4-2 system register map bit 0 at address 7eh and all four bits at address 7fh (psw) are assigned to the program status word. the bcd flag is mapped in bit 0 at address 7eh, the cmp flag is mapped in bit 3 at address 7fh, the cy flag is mapped in bit 2, and the z flag is mapped in bit 1 at address 7fh. the high-order three bits at address 7eh and bit 0 at address 7fh are always set to 0. address data 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh 00 000 0 0000 7eh 7fh psword 0 0 0 0 bit 0 bit 3 bit 2 bit 1 bit 0 b c d c m p c y z addresses 74h to 7dh are always set to 0. psw 15 m pd17107(a1) fig. 4-3 configuration of the program status word comparison instructions (ske, skne, skge, or sklt) do not change the state of the cy flag, but an arithmetic operation may affect the cy flag according to the result even if the cmp flag is set. each bit of the program status word is initialized to 0 when a reset signal is applied. the z flag in the program status word changes according to the set value of the cmp flag as listed in table 4-1. psw 0 address 7eh address 7fh bit 0 bit 3 bit 0 zero flag (z) set to 1 when: ? an arithmetic operation generates a result of zero if cmp = 0. ? an arithmetic operation generates a result of zero and z = 1 if cmp = 1. when the z flag is already 0, it remains unchanged. reset to 0 when: ? an arithmetic operation generates a result other than zero. carry flag (cy) set to 1 when: ? an addition produces a carry or a subtraction produces a borrow. ? the lsb of the operand in the rorc instruction is 1. reset to 0 when: ? neither a carry nor borrow is produced. ? the lsb of the operand in the rorc instruction is 0. compare flag (cmp) if this flag is set, the result of an arithmetic operation is not stored in memory or general registers. the flag is automatically reset by executing the skt or skf instruction. bcd flag (bcd) if this flag is set, arithmetic operations are performed in decimal, and if this flag is reset, arithmetic operations are performed in binary. bcd cmp cy z 16 m pd17107(a1) table 4-1 change in z flag while cmp is 1, if an arithmetic operation results in 0h when the value of the z flag is 1, the z flag does not change. if an arithmetic operation results in other than 0h, the z flag is reset to 0 and remains intact even when a second arithmetic operation results in 0h. after the cmp and z flags are set to 1, subtraction and comparison are performed several times. then, if the z flag still indicates 1, all of the comparison operations showed a match, resulting in 0. if the z flag is 0 after the comparison operations, a mismatch occurred in at least one comparison operation. example of 12-bit data comparison ; is the 12-bit data stored in m001, m002, and m003 equal to 456h? cmp456: set2 cmp, z sub m001, #4 ; stores the data in m001, m002, and m003. sub m002, #5 ; does not damaged the data. sub m003, #6 ; ; clr1 cmp skt1 z ; resets cmp automatically when the bit test instruction is executed. br differ ; 456h br agree ; = 456h when arithmetic operation results in 0 when arithmetic operation results in a non-zero value conditions z 1 z 0 z flag does not change z 0 cmp = 0 cmp = 1 17 m pd17107(a1) 5. alu block the alu is used for performing arithmetic operations, logical operations, bit evaluations, comparison evaluations, and rotations on 4-bit data. 5.1 alu block configuration fig. 5-1 shows the configuration of the alu block. as shown in fig. 5-1, the alu block consists of the main 4-bit data processor, temporary registers a and b, the status flip-flop for controlling the status of the alu, and the decimal conversion circuit for use during arithmetic operations in bcd. as shown in fig. 5-1, the status flip-flop consists of the following flags: zero flag flip-flop, carry flag flip-flop, compare flag flip-flop, and the bcd flag flip-flop. each flag in the status flip-flop corresponds directly to a flag in the program status word (psword: addresses 7eh, 7fh) located in the system register. the flags in the program status word are the following: zero flag (z), carry flag (cy), compare flag (cmp), and the bcd flag (bcd). 5.2 functions of the alu block arithmetic operations, logical operations, bit evaluations, comparison evaluations, and rotations are performed using the instructions in the alu block. table 5-1 lists each arithmetic/logical instruction, evaluation instruction, and rotation instruction. by using the instructions listed in table 5-1, 4-bit arithmetic/logical operations, evaluations and rotations can be performed in a single instruction. arithmetic operations in bcd can also be performed on one place in a single instruction. 5.2.1 functions of the alu the arithmetic operations consist of addition and subtraction. arithmetic operations can be performed on the contents of the general register and data memory or on immediate data and the contents of data memory. operations in binary are performed on four bits of data and operations in bcd are performed on one place. logical operations include anding, oring, and xoring. their operands can be general register contents and data memory contents, or data memory contents and immediate data. bit evaluation is used to determine whether bits in 4-bit data in data memory are 0 or 1. comparison evaluation is used to compare contents of data memory with immediate data. it is used to determine whether one value is equal to or greater than the other, less than the other, or if both values are equal or not equal. rotation is used to shift 4-bit data in the general register one bit in the direction of its least significant bit (rotation to the right). 18 m pd17107(a1) fig. 5-1 configuration of the alu block data bus temporary register a temporary register b status flip-flop alu ? arithmetic operations ? logical operations ? bit evaluations ? comparison evaluations ? rotations decimal con- version circuit 7eh b 0 bcd b 3 b 2 b 1 b 0 cmp cy z 0 7fh program status word (psword) address name bit flag status flip-flop bcd flag flip-flop cmp flag flip-flop cy flag flip-flop z flag flip-flop function outline indicates when the result of an arithmetic operation is 0. stores the borrow or carry from an arithmetic operation. used to indicate whether to store the result of an arithmetic operation. used to indicate whether to perform bcd correction for arithmetic operations. 19 m pd17107(a1) [memo] 20 m pd17107(a1) table 5-1 list of alu instructions (1/2) alu function instruction operation explanation addi- tion sub- traction logical or logical and logical xor true false equal not equal < rotate to the right add r, m add m, #n4 addc r, m addc m, #n4 sub r, m sub m, #n4 subc r, m subc m, #n4 or r, m or m, #n4 and r, m and m, #n4 xor r, m xor m, #n4 skt m, #n skf m, #n ske m, #n4 skne m, #n4 skge m, #n4 sklt m, #n4 rorc r arithme- tic opera- tions logical opera- tions bit evalua- tion compari- son evalua- tion rotation (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + cy (m) (m) + n4 + cy (r) (r) C (m) (m) (m) C n4 (r) (r) C (m) C cy (m) (m) C n4 C cy (r) (r) M (m) (m) (m) M n4 (r) (r) ? (m) (m) (m) ? n4 (r) (r) M (m) (m) (m) M n4 cmp 0, if (m) ? n = n, then skip cmp 0, if (m) ? n = 0, then skip (m) C n4, skip if zero (m) C n4, skip if not zero (m) C n4, skip if not borrow (m) C n4, skip if borrow adds contents of general register and data memory. result is stored in general register. adds immediate data to contents of data memory. result is stored in data memory. adds contents of general register, data memory and carry flag. result is stored in general register. adds immediate data, contents of data memory and carry flag. result is stored in data memory. subtracts contents of data memory from contents of general register. result is stored in general register. subtracts immediate data from data memory. result is stored in data memory. subtracts contents of data memory and carry flag from contents of general register. result is stored in general register. subtracts immediate data and carry flag from data memory. result is stored in data memory. or operation is performed on contents of general register and data memory. result is stored in general register. or operation is performed on immediate data and contents of data memory. result is stored in data memory. and operation is performed on contents of general register and data memory. result is stored in general register. and operation is performed on immediate data and contents of data memory. result is stored in data memory. xor operation is performed on contents of general register and data memory. result is stored in general register. xor operation is performed on immediate data and contents of data memory. result is stored in data memory. skips next instruction if all bits in data memory specified by n are true (1). result is not stored. skips next instruction if all bits in data memory specified by n are false (0). result is not stored. skips next instruction if immediate data equals contents of data memory. result is not stored. skips next instruction if immediate data is not equal to contents of data memory. result is not stored. skips next instruction if contents of data memory is greater than or equal to immediate data. result is not stored. skips next instruction if contents of data memory is less than immediate data. result is not stored. rotate contents of the general register along with the cy flag to the right. result is stored in general register. (cy) ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 21 m pd17107(a1) table 5-1 list of alu instructions (2/2) alu function operation depending on the program status word (psword) value in bcd flag value in cmp flag operation z flag 0 0 store result of binary operation set (1) when result of operation is 0000b, otherwise reset (0). 0 1 do not store result of binary operation status maintained when result of operation is 0000b, otherwise reset (0). 1 0 store result of decimal operation set (1) when result of operation is 0000b, otherwise reset (0). 11 do not store result of decimal operation status maintained when result of operation is 0000b, otherwise reset (0). dont care (maintained) dont care (maintained) no change dont care (maintained) dont care (main- tained) cy flag dont care (maintained) reset no change dont care (maintained) dont care (maintained) dont care (maintained) no change dont care (maintained) dont care (maintained) dont care (maintained) no change dont care (maintained) value in b 0 of the gen- eral register set (1) when carry or borrow is gener- ated, otherwise reset (0). dont care (main- tained) dont care (main- tained) arithmetic operation rotation comparison evaluation bit evaluation logical operations 22 m pd17107(a1) 5.2.2 functions of temporary registers a and b temporary registers a and b are needed for processing of 4-bit data. these registers are used for temporary storage of the first and second data operands of an instruction. 5.2.3 functions of the status flip-flop the status flip-flop is used for controlling operation of the alu and for storing data which has been processed. each flag in the status flip-flop corresponds directly to a flag in the program status word (psword) located in the system register. this means that when a flag in the system register is manipulated it is the same as manipulating a flag in the status flip-flop. each flag in the program status word is described below. (1) z flag this flag is set (1) when the result of an arithmetic operation is 0000b, otherwise it is reset (0). however, as described below, depending on the status of the cmp flag, the conditions which cause this flag to be set (1) can be changed. (i) when cmp = 0 z flag is set (1) when the result of an arithmetic operation is 0000b, otherwise it is reset (0). (ii) when cmp = 1 the previous state of the z flag is maintained when the result of an arithmetic operation is 0000b, otherwise it is reset (0). only affected by arithmetic operations. (2) cy flag this flag is set (1) when a carry or borrow is generated in the result of an arithmetic operation, otherwise it is reset (0). when an arithmetic operation is being performed using a carry or borrow, the operation is performed using the cy flag as the least significant bit. when a rotation (rorc instruction) is performed, the contents of the cy flag becomes the most significant bit (bit b 3 ) of the general register and the least significant bit of the general register is stored in the cy flag. only affected by arithmetic operations and rotations. (3) cmp flag when the cmp flag is set (1), the result of an arithmetic operation is not stored in either the general register or data memory. when the bit evaluation instruction is performed, the cmp flag is reset (0). the cmp flag does not affect comparison evaluations, logical operations, or rotations. (4) bcd flag when the bcd flag is set (1), all arithmetic operations are performed in bcd. when the flag is reset (0), all operations are performed in 4-bit binary. the bcd flag does not affect logical operations, bit evaluations, comparison evaluations, or rotations. these flags can also be set through direct manipulation of the values in the program status word (psword). when the flags in the program status word are manipulated, the corresponding flag in the status flip-flop is also manipulated. 23 m pd17107(a1) 5.2.4 performing operations in 4-bit binary when the bcd flag is set to 0, arithmetic operations are performed in 4-bit binary. 5.2.5 performing operations in bcd when the bcd flag is set to 1, arithmetic operations are performed in bcd. table 5-2 shows the differences in the results of operations performed in 4-bit binary and in bcd. when the result of an addition in bcd is equal to or greater than 20, or the result of a subtraction in bcd is outside of the range -10 to +9, a value of 1010b (0ah) or higher is stored as the result (shaded area in table 5-2). table 5-2 results of arithmetic operations performed in 4-bit binary and bcd addition in bcd operation result 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1110 1111 1100 1101 1110 1111 1100 1101 1010 1011 1100 1101 addition in 4-bit binary operation result subtraction in 4-bit binary subtraction in bcd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 1110 1111 1100 1101 1110 1111 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 operation result operation result cy cy operation result cy cy operation result 24 m pd17107(a1) 5.2.6 performing operations in the alu block when arithmetic operations, logical operations, bit evaluations, comparison evaluations or rotations in a program are executed, the first data operand is stored in temporary register a and the second data operand is stored in temporary register b. the first data operand is four bits of data used to specify the contents of an address in the general register or data memory. the second data operand is four bits of data used to either specify the contents of an address in data memory or to be used as an immediate value. for example, in the instruction add r, m second data operand first data operand the first data operand, r, is used to specify the contents of an address in the general register. the second data operand, m, is used to specify the contents of an address in data memory. in the instruction add m, #n4 the first data operand, m, is used to specify an address in data memory. the second operand, #n4, is immediate data. in the rotation instruction rorc r only the first data operand, r (used to specify the contents of an address in the general register) is used. next, using the data stored in temporary registers a and b, the alu executes the operation specified by the instruction (arithmetic operation, logical operation, bit evaluation, comparison evaluation, or rotation). when the instruction being executed is an arithmetic operation, logical operation, or rotation, the data processed by the alu is stored in the location specified by the first data operand (general register address or data memory address) and the operation terminates. when the instruction being executed is a bit evaluation or comparison evaluation, the result processed by the alu is used to determine whether or not to skip the next instruction (whether to treat next instruction as a no operation instruction: nop) and the operation terminates. caution should be taken with regard to the following points: (1) arithmetic operations are affected by the cmp and bcd flags in the program status word. (2) logical operations are not affected by the cmp or bcd flag in the program status word. logical operations do not affect the z or cy flags. (3) bit evaluation causes the cmp flag in the program status word to be reset. 25 m pd17107(a1) 5.3 arithmetic operations (addition and subtraction in 4-bit binary and bcd) as shown in table 5-3, arithmetic operations consist of addition, subtraction, addition with carry, and subtraction with borrow. these instructions are add, addc, sub, and subc. the add, addc, sub, and subc instructions are further divided into addition and subtraction of the general register and data memory and addition and subtraction of data memory and immediate data. when the operands r and m are used, addition or subtraction is performed using the general register and data memory. when the operands m and #n4 are used, addition or subtraction is performed using data memory and immediate data. arithmetic operations are affected by the status flip-flop and the program status word (psword) in the system register. the bcd flag in the program status word (psword) is used to specify whether arithmetic operations are to be performed in 4-bit binary or in bcd. the cmp flag is used to specify whether or not the results of arithmetic operations are to be stored. sections 5.3.1 to 5.3.4 explain the relationship between each command and the program status word (psword). table 5-3 types of arithmetic operations 5.3.1 addition and subtraction when bcd = 0 and cmp = 0 addition and subtraction are performed in 4-bit binary and the result is stored in the general register (or data memory). when the result of the operation is greater than 1111b (carry generated) or less than 0000b (borrow generated), the cy flag is set (1); otherwise it is reset (0). when the result of the operation is 0000b, the z flag is set (1) regardless of whether there is carry or borrow; otherwise it is reset (0). 5.3.2 addition and subtraction when bcd = 0 and cmp = 1 addition and subtraction are performed in 4-bit binary. however, because the cmp flag is set (1), the result of the operation is not stored in either the general register (or data memory). when there is a carry or borrow in the result of the operation, the cy flag is set (1); otherwise it is reset (0). when the result of the operation is 0000b, the previous state of the z flag is maintained; otherwise it is reset (0). without carry add with carry addc without borrow sub with borrow subc general register and data memory add r, m data memory and immediate data add m, #n4 general register and data memory addc r, m data memory and immediate data addc m, #n4 general register and data memory sub r, m data memory and immediate data sub m, #n4 general register and data memory subc r, m data memory and immediate data subc m, #n4 addition subtraction arithmetic operation 26 m pd17107(a1) 5.3.3 addition and subtraction when bcd = 1 and cmp = 0 bcd operations are performed. the result of the operation is stored in the general register (or data memory). when the result of the operation is greater than 1001b (9d) or less than 0000b (0d), the carry flag is set (1), otherwise it is reset (0). when the result of the operation is 0000b (0d), the z flag is set (1), otherwise it is reset (0). operations in bcd are performed by first computing the result in binary and then by using the decimal conversion circuit to convert the result to decimal. for information concerning the binary to decimal conversion, see table 5- 2 in section 5.2.5 . in order for operations in bcd to be performed properly, note the following: (1) result of an addition must be in the range 0d to 19d. (2) result of a subtraction must be in the range 0d to 9d, or in the range -10d to -1d. the following shows which value is considered the cy flag in the range 0d to 19d (shown in hexadecimal): 0, 0000b to 1, 0011b cy cy the following shows which value is considered the cy flag in the range -10d to -1d (shown in hexadecimal): 1, 0110b to 1, 1111b cy cy when operations in bcd are performed outside of the limits of (1) and (2) stated above, the cy flag is set (1) and the result of operation is output as a value greater than or equal to 1010b (0ah). 5.3.4 addition and subtraction when bcd = 1 and cmp = 1 bcd operations are performed. the result is not stored in either the general register (or data memory). example set2 bcd, cmp ; sets the bcd flag and cmd flag (1). add pegx, memx ; adds the register regx and data memory memx. clr1 bcd ; clears the bcd flag (0). skt1 cy ; checks the cy flag and clears the cmp flag (0). br under10 ; regx + memx < 10 br over10 ; regx + memx 10 in this example, the alu checks whether the sum of the register regx and data memory memx is greater than or equal to 10, without corrupting the contents of regx and memx. 27 m pd17107(a1) 5.3.5 warnings concerning use of arithmetic operations when performing arithmetic operations with the psw (address 7fh), note the followings: when the cmp flag is cleared (0) and an arithmetic operation is performed on the psw, the result is stored in the psw. this means that there is no way to check the cy and z flags in the psw. however, when the cmp flag is set (1), results of arithmetic operations are not stored. therefore, even in the above case, the cy and z flags can be checked. 5.4 logical operations as shown in table 5-4, logical operations consist of logical or, logical and, and logical xor. accordingly, the logical operation instructions are or, and, and xor. the or, and, and xor instructions can be performed on either the general register and data memory, or on data memory and immediate data. the operands of these instructions are specified in the same way as for arithmetic operations ("r, m" or "m, #n4"). logical operations are not affected by the bcd or cmp flags in the program status word (psword). the operations do not affect the cy and z flags at all. table 5-4 logical operations table 5-5 table of true values for logical operations logical and c = a and b logical or c = a or b logical xor c = a xor b general register and data memory or r, m data memory and immediate data or m, #n4 general register and data memory and r, m data memory and immediate data and m, #n4 general register and data memory xor r, m data memory and immediate data xor m, #n4 logical or logical and logical xor logical operation a 0 0 1 1 a 0 0 1 1 b 0 1 0 1 c 0 0 0 1 b 0 1 0 1 c 0 1 1 1 a 0 0 1 1 b 0 1 0 1 c 0 1 1 0 28 m pd17107(a1) 5.5 bit evaluations as shown in table 5-6, there are both true (1) and false (0) bit evaluation instructions. the skt instruction skips the next instruction when a bit is evaluated as true (1) and the skf instruction skips the next instruction when a bit is evaluated as false (0). the skt and skf instructions can only be used with data memory. bit evaluations are not affected by the bcd flag in the program status word (psword). the evaluations do not affect the cy and z flags at all. however, when an skt or skf instruction is executed, the cmp flag is reset (0). sections 5.5.1 and 5.5.2 explain true (1) and false (0) bit evaluations. table 5-6 bit evaluation instructions 5.5.1 true (1) bit evaluation the true (1) bit evaluation instruction (skt m, #n) is used to determine whether or not the bits specified by n in the four bits of data memory m are true (1). when all bits specified by n are true (1), this instruction causes the next instruction to be skipped. example mov m1, #1011b skt m1, #1011b ; 1 br a br b skt m1, #1101b ; 2 br c br d in this example, bits b 3 , b 1 , and b 0 of data memory m1 are evaluated in step number 1 . because all the bits are true (1), the program branches to b. in step number 2 , bits b 3 , b 2 , and b 0 of data memory m1 are evaluated. since b 2 of data memory m1 is false (0), the program branches to c. true (1) bit evaluation skt m, #n false (0) bit evaluation skf m, #n bit evaluation 29 m pd17107(a1) 5.5.2 false (0) bit evaluation the false (0) bit evaluation instruction (skf m, #n) is used to determine whether or not the bits specified by n in the four bits of data memory m are false (0). when all bits specified by n are false (0), this instruction causes the next instruction to be skipped. example mov m1, #1001b skf m1, #0110b ; 1 br a br b skf m1, #1110b ; 2 br c br d in this example, bits b 2 and b 1 of data memory m1 are evaluated in step number 1 . because both bits are false (0), the program branches to b. in step number 2 , bits b 3 , b 2 , and b 1 of data memory m1 are evaluated. since b 3 of data memory m1 is true (1), the program branches to c. 5.6 comparison evaluations as shown in table 5-7, there are comparison evaluation instructions for determining if one value is "equal to," "not equal to," "greater than or equal to," or "less than" another. the ske instruction is used to determine if two values are equal. the skne instruction is used to determine two values are not equal. the skge instruction is used to determine if one value is greater than or equal to another and the sklt instruction is used to determine if one value is less than another. the ske, skne, skge, and sklt instructions perform comparisons between a value in data memory and immediate data. in order to compare values in the general register and data memory, a subtraction instruction is performed according to the values in the cmp and z flags in the program status word (psword). for more information concerning comparison of the general register and data memory, see section 5.3 . comparison evaluations are not affected by the bcd or cmp flags in the program status word (psword). the evaluations do not affect the cy and z flags at all. sections 5.6.1 to 5.6.4 explain the "equal," "not equal," "greater than or equal," and "less than" comparison evaluations. table 5-7 comparison evaluation instructions equal ske m, #n4 not equal skne m, #n4 greater than or equal skge m, #n4 less than sklt m, #n4 comparison evaluation 30 m pd17107(a1) 5.6.1 "equal" evaluation the "equal" evaluation instruction (ske m, #n4) is used to determine if immediate data and the contents of a location in data memory are equal. this instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are equal. example mov m1, #1010b ske m1, #1010b ; 1 br a br b ske m1, #1000b ; 2 br c br d in this example, because the contents of data memory m1 and immediate data 1010b in step number 1 are equal, the program branches to b. in step number 2 , because the contents of data memory m1 and immediate data 1000b are not equal, the program branches to c. 5.6.2 "not equal" evaluation the "not equal" evaluation instruction (skne m, #n4) is used to determine if immediate data and the contents of a location in data memory are not equal. this instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are not equal. example mov m1, #1010b skne m1, #1000b ; 1 br a br b skne m1, #1010b ; 2 br c br d in this example, because the contents of data memory m1 and immediate data 1000b in step number 1 are not equal, the program branches to b. in step number 2 , because the contents of data memory m1 and immediate data 1010b are equal, the program branches to c. 31 m pd17107(a1) 5.6.3 "greater than or equal" evaluation the "greater than or equal" evaluation instruction (skge m, #n4) is used to determine if the contents of a location in data memory is a value greater than or equal to the value of the immediate data operand. if the value in data memory is greater than or equal to that of the immediate data, this instruction causes the next instruction to be skipped. example mov m1, #1000b skge m1, #0111b ; 1 br a br b skge m1, #1000b ; 2 br c br d skge m1, #1001b ; 3 br e br f in this example, the program will first branch to b since the value in data memory is larger than that of the immediate data ( 1 ). next it will branch to d since the value in data memory is equal to that of the immediate data ( 2 ). last it will branch to e since the value in data memory is less than that of the immediate data ( 3 ). 5.6.4 "less than" evaluation the "less than" evaluation instruction (sklt m, #n4) is used to determine if the contents of a location in data memory is a value less than that of the immediate data operand. if the value in data memory is less than that of the immediate data, this instruction causes the next instruction to be skipped. example mov m1, #1000b sklt m1, #1001b ; 1 br a br b sklt m1, #1000b ; 2 br c br d sklt m1, #0111b ; 3 br e br f in this example, the program will first branch to b since the value in data memory is less than that of the immediate data ( 1 ). next it will branch to c since the value in data memory is equal to that of the immediate data ( 2 ). last it will branch to e since the value in data memory is greater than that of the immediate data ( 3 ). 32 m pd17107(a1) 5.7 rotations there are rotation instructions for rotation to the right and for rotation to the left. the rorc instruction is used for rotation to the right. the rorc instruction can only be used with the general register. rotation using the rorc instruction is not affected by the bcd or cmp flags in the program status word (psword). the rotation does not affect the z flag at all. rotation to the left is performed by using the addition instruction addc. sections 5.7.1 and 5.7.2 explain rotation. 5.7.1 rotation to the right the instruction used for rotation to the right (rorc r) rotates the contents of the general register in the direction of its least significant bit. when this instruction is executed, the contents of the cy flag becomes the most significant bit of the general register (bit b 3 ) and the least significant bit of the general register (bit b 0 ) is placed in the cy flag. examples 1. mov psw, #0100b ; sets cy flag to 1. mov r1, #1100b rorc r1 when these instructions are executed, the following operation is performed. basically, when rotation to the right is performed, the following operation is executed: cy flag ? b 3 , b 3 ? b 2 , b 2 ? b 1 , b 1 ? b 0 , b 0 ? cy flag. 2. mov psw, #0000b ; resets cy flag to 0. mov r1, #1000b ; most significant bit mov r2, #0100b mov r3, #0010b ; least significant bit rorc r1 rorc r2 rorc r3 the program code above rotates 13 bits in cy, r1, r2, and r3 to the right. cy flag b 3 b 2 b 1 b 0 1 110 0 33 m pd17107(a1) 5.7.2 rotation to the left rotation to the left is performed by using the addition instruction, "addc r, m". example mov psw, #0000b ; resets cy flag to 0. mov r1, #1000b ; most significant bit mov r2, #0100b mov r3, #0010b ; least significant bit addc r3, r3 addc r2, r2 addc r1, r1 skf1 cy or r3, #0001b the program code above rotates 13 bits in cy, r1, r2, and r3 to the left. 34 m pd17107(a1) 6. ports 6.1 port 0b (p0b 0 /rls halt , p0b 1 /rls stop , p0b 2 ) port 0b is a three-bit input/output port. only n-ch open-drain outputs appear on the pins of port 0b. the n-ch open-drain output mode allows application of 9 v, so it can be used for interfacing with a circuit operating on a different power supply voltage. input and output are set in units of nibbles. the input mode is set at reset, and the output mode is set by writing data to the port register in address 71h of the data memory. the output mode is maintained until the system is reset. output to the port is executed via the port register. once data is written to the port register, all pins of port 0b are placed in the output mode to continue to output written data. the data is retained unless new data is written to the register. writing 1 to the port register makes the n-ch open-drain output pin high-impedance. therefore, the pin which outputs 1 can be used as an input pin. whenever the port register is read, the read data indicates the states of the pins note , not the contents of the port register, regardless of whether the pins are in the input or output mode. in this case, the contents of the port register remain unchanged. the port register for port 0b consists of four bits but its highest bit is always set to 0. this means that if an attempt is made to write data to the highest bit of 71h, the data is invalidated and if an attempt is made to read it, 0 is always returned. a p0b 0 input signal releases the halt mode as a pseudo interrupt. a p0b 1 input signal releases the stop mode as a pseudo interrupt. (see chapter 7 .) 6.2 port 0c (p0c 0 to p0c 3 ) port 0c is a four-bit input/output port. cmos (push-pull) outputs appear on those pins. input and output are set in units of nibbles. the input mode is set at reset, and the output mode is set by writing data to the port register in address 72h of the data memory. the output mode is maintained until the system is reset. output to the port is executed via the port register. once data is written to the port register, all pins of the port 0c are placed in the output mode to continue to output written data. the data is retained unless new data is written to the register. whenever the port register is read, the read data indicates the states of the pins note , not the contents of the port register, regardless of whether the pins are in the input or output mode. in this case, the contents of the port register remain unchanged. 6.3 port 0d (p0d 0 to p0d 3 ) port 0d is a four-bit input/output port. cmos (push-pull) outputs appear on these pins. input and output are set in units of nibbles. the input mode is set at reset, and the output mode is set by writing data to the port register in address 73h of the data memory. the output mode is maintained until the system is reset. output to the port is executed via the port register. once data is written to the port register, all pins of the port 0d are placed in the output mode to continue to output written data. the data is retained until new data is written to the register. whenever the port register is read, the read data indicates the states of the pins note , not the contents of the port register, regardless of whether the pins are in the input or output mode. in this case, the contents of the port register remain unchanged. note in the output mode, design an external circuit appropriately depending on the output data. 35 m pd17107(a1) column address 01 23 45 67 89abcdef 0x 7x row address address bit symbol port register system register 70h 71h 72h 73h p 0 b 2 p 0 b 1 p 0 b 0 p 0 c 3 p 0 c 2 p 0 c 1 p 0 c 0 p 0 d 3 p 0 d 2 p 0 d 1 p 0 d 0 always set to 0 00000 fig. 6-1 port register map 36 m pd17107(a1) 6.4 notes on manipulating port registers the states of the i/o port pins of the m pd17107(a1) can be read even when the port pins have been set to output mode. when a port register is manipulated with a built-in macro instruction (such as setn or clrn) or and, or, or xor instruction, the states of those pins for which the state should remain unchanged may change unexpectedly. especially when using some of the port 0b pins (n-ch open-drain outputs) as input pins, with the remaining port 0b pins being used as output pins, always take the possibility of this change in the states of the pins into consideration. when a clr1 p0b2 instruction (identical to an and 71h, #1011b instruction) is applied to the port 0b pins, the corresponding port register and internal states are changed, as shown in fig. 6-2. assume that the states of port 0b are those shown in fig. 6-2 1 . pins p0b 3 and p0b 2 , used as output pins, output high level, while pins p0b 1 and p0b 0 , used as input pins, receive low level. it is required that high level be output, inside the chip, from the port 0b pins to be used as input pins. although the m pd17103, m pd17103l, m pd17107, and m pd17107l do not support pin p0b 3 , it is virtually assumed to exist within a program. when a clr1 p0b2 instruction is executed to set pin p0b 2 to low, the states of the port 0b pins change as shown in fig. 6-2 2 . the port register changes such that pins p0b 1 and p0b 0 , required to output high level, actually output low level. this is because the clr1 p0b2 instruction has been applied to the states of the port 0b pins, but not to the states of the port register. to prevent this problem, use another instruction, such as a mov instruction, to specify the states of all port 0b pins, not merely the states of those pins whose states are to be changed. in this example, it is recommended that a mov 71h, #1011b instruction be used to set only pin p0b 2 to low. fig. 6-2 changes in the port register according to the execution of a clr1 p0b2 instruction state before the instruction is executed after the instruction is executed internal pin p0b 3 p0b 2 p0b 1 p0b 0 port register 1111 h output h output h output h output h h l (input) l (input) executing a clr1 p0b2 instruction [and 71h, #1011b] state internal pin p0b 3 p0b 2 p0b 1 p0b 0 port register 1000 h output l output l output l output hlll h: high level, l: low level 1 2 37 m pd17107(a1) 7. standby functions the m pd17107(a1) provides two standby modes, the halt mode and the stop mode. 7.1 halt mode the halt mode stops the program counter (pc) while allowing the system clock to continue operating. the halt mode can be entered with the halt instruction, and can be released by a reset signal (reset) or high-level input to the p0b 0 pin. when the halt mode is released by a high-level signal input to the p0b 0 pin, the system does not wait for the system clock oscillation to settle. the instruction immediately after the halt instruction is executed. when the halt mode is released forcibly by the reset signal (reset), normal reset occurs, and the program starts at address 0h. 7.2 stop mode the stop mode stops the system clock oscillation so that data can be retained at low power voltage. the stop mode can be entered with the stop instruction, and can be released by a reset signal (reset) or high-level input to the p0b 1 pin. when the mode is released by a high-level signal input to the p0b 1 pin, the program starts with the instruction immediately after the stop instruction. when the stop mode is released forcibly by the reset signal (reset), normal reset occurs, and the program starts at address 0h. 7.3 setting and releasing the standby modes (1) setting and releasing the halt mode conditions for releasing the halt mode are selected with the least significant bit of the operand in the halt instruction as shown in table 7-1. the high-order three bits of the operand must be set to 0. table 7-1 conditions for setting/releasing the halt mode halt 000 xb 4-bit data in the operand (2) setting and releasing the stop mode conditions to release the stop mode are selected with the least significant bit of the operand in the stop instruction as shown in table 7-2. the high-order three bits of the operand must be set to 0. conditions for setting/releasing the halt mode x after executing a halt instruction, the system enters the halt mode unconditionally. the mode can be released only by the reset signal (reset). after the mode is released, the program starts at address 0h. when a halt instruction is executed with the p0b 0 pin being at low level, the system enters the halt mode. the mode can be released by the reset signal (reset). when the mode is released, the program starts at address 0h. this mode can also be released when a high-level signal is applied to the p0b 0 pin. in this case, the program starts with the instruction immediately after the halt instruction. when a halt instruction is executed with the p0b 0 pin being at high level, the instruction is ignored (regarded as a nop instruction) and the system does not enter the halt mode. 0 1 38 m pd17107(a1) table 7-2 conditions for setting/releasing the stop mode stop 000 xb 4-bit data in the operand 7.4 hardware statuses in standby mode hardware statuses in standby mode are as follows: table 7-3 hardware statuses in standby mode 7.5 timing for releasing the standby modes fig. 7-1 releasing the halt mode by reset input when the reset signal is applied to release the halt mode, the reset input makes a transition from low to high, then an operation mode is entered. note the halt mode remains effective in this period, waiting for the operation mode. an operation starts after eight clock pulses on the osc 0 pin are counted. conditions for setting/releasing the stop mode x 0 1 after executing a stop instruction, the system enters the stop mode unconditionally. all peripheral circuits are placed in the same initial state as when the system is reset, then they stop operat- ing. the mode can be released only by the reset signal (reset). after the mode is released, the program starts at address 0h. when a stop instruction is executed with the p0b 1 pin being at low level, the system enters the stop mode. the mode can be released by the reset signal (reset). when the mode is released, the program starts at address 0h. this mode can also be released when a high-level signal is applied to the p0b 1 pin. in this case, the program starts with the instruction immediately after the stop instruction. when a stop instruction is executed with the p0b 1 pin being at high level, the instruction is ignored (regarded as a nop instruction) and the system does not enter the stop mode. oscillation disabled 000h previous data is retained. all bits are set to 0. previous data is retained. (all pins are placed in input mode.) halt instruction: oscillation continued stop instruction: oscillation disabled address following a halt or stop instruction is indicated. previous data is retained. previous data is retained. previous data is retained. (input/output mode of pins is also retained.) clock generator program counter data memory (00h to 0fh) program status word (psword) port register (71h to 73h) hardware halt or stop 0001b instruction stop 0000b instruction halt instruction reset clock operation mode oscillation note operation mode halt mode 39 m pd17107(a1) fig. 7-2 releasing the halt mode by high-level input to the p0b 0 pin fig. 7-3 releasing the stop mode by reset input as soon as the reset input makes a transition from high to low in the stop mode, the system clock starts generating clock pulses. note the halt mode remains effective in this period, waiting for the generation of clock pulses to settle. an operation starts after eight clock pulses on the osc 0 pin are counted. fig. 7-4 releasing the stop mode by high-level input to the p0b 1 pin note the halt mode remains effective in this period, waiting for the generation of clock pulses to settle. an operation starts after eight clock pulses on the osc 0 pin are counted. halt instruction clock operation mode oscillation operation mode halt mode standby release signal (p0b 0 ) stop instruction operation mode oscillation operation mode halt mode stop mode reset clock oscillation note oscillation stopped stop instruction operation mode oscillation operation mode clock oscillation note oscillation stopped stop instruction standby release signal (p0b 1 ) 40 m pd17107(a1 ) 8. reset function 8.1 reset function a low-level signal, applied to the reset pin, resets the system, then the hardware is initialized. the system clock oscillates as long as the power supply voltage is supplied, even if a low-level signal is applied to the reset pin. a low to high transition on the reset pin releases the reset status and causes the system to enter the operating mode once the 8-clock oscillation settling wait time has elapsed. table 8-1 hardware status after reset note the hardware is initialized when the stop 0000b instruction is executed. input/output mode output latch program counter data memory (00h to 0fh) program status word (psword) port 000h undefined all bits are set to 0. input undefined 000h data existing before reset is retained. all bits are set to 0. input data existing before reset is retained. ? reset immediately after power on ? reset during operation hardware reset in standby mode note 41 m pd17107(a1) 9. reserved words used in assembly language 9.1 mask-option pseudo instructions source programs in the assembly language for the m pd17107(a1) must include mask-option pseudo instructions to select pin options. to do this, be sure to catalog the d17107.opt file in as17103 (device file for the m pd17107(a1)) into the current directory beforehand. specify mask options for the following pins: ? p0b 0 ? p0b 1 ? p0b 2 ? reset 9.1.1 option and endop pseudo instructions the part starting with the option pseudo instruction and ending with the endop pseudo instruction is referred to as a mask-option definition block. the coding format of the mask-option definition block is as follows. only the two pseudo instructions listed in table 9-1 can be coded in the block. format: symbol mnemonic operand comment [label:] option [;comment] ? ? ? endop 9.1.2 mask-option definition pseudo instructions table 9-1 lists the pseudo instructions to define a mask option for each pin. table 9-1 mask-option definition pseudo instructions the coding format of optp0b is as follows. to define the mask option, specify p0b 2 (first operand), p0b 1 , and p0b 0 in the operand field. format: symbol mnemonic operand comment [label:] optp0b (p0b 2 ),(p0b 1 ),(p0b 0 ) [;comment] number of operands mask-option pseudo instruction operand pin p0bplup (pull-up resistor provided) open (no pull-up resistor provided) resplup (pull-up resistor provided) open (no pull-up resistor provided) p0b 2 - p0b 0 reset optp0b optres 3 1 42 m pd17107(a1 ) the coding format of optres is as follows. format: symbol mnemonic operand comment [label:] optres (reset) [;comment] example the following mask options are set in a m pd17107(a1) source file to be assembled: p0b 2 : pull-up, p0b 1 : open, p0b 0 : open reset: pull-up ? ? ? ;17107(a1) setting mask options: option optp0b p0bplup, open, open optres resplup endop ? ? ? 43 m pd17107(a1) 9.2 reserved symbols table 9-2 lists the reserved symbols defined in the m pd17107(a1) device file (as17103). table 9-2 reserved symbols r/w: read/write note although a pin corresponding to p0b3 does not exist in the m pd17107(a1), p0b3 is defined as a read-only flag so that it is used in a built-in macro. name value attribute r/w description 0.71h.0 0.71h.1 0.71h.2 0.71h.3 0.72h.0 0.72h.1 0.72h.2 0.72h.3 0.73h.0 0.73h.1 0.73h.2 0.73h.3 0.7eh.0 0.7fh 0.7fh.1 0.7fh.2 0.7fh.3 flg flg flg flg flg flg flg flg flg flg flg flg flg mem flg flg flg r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w p0b0 p0b1 p0b2 p0b3 note p0c0 p0c1 p0c2 p0c3 p0d0 p0d1 p0d2 p0d3 bcd psw z cy cmp bit 0 of port 0b bit 1 of port 0b bit 2 of port 0b always set to 0 bit 0 of port 0c bit 1 of port 0c bit 2 of port 0c bit 3 of port 0c bit 0 of port 0d bit 1 of port 0d bit 2 of port 0d bit 3 of port 0d bcd arithmetic flag program status word zero flag carry flag compare flag 44 m pd17107(a1 ) 10. instruction set 10.1 instruction set list b 14 -b 11 0 1 1 1 7 0 1 hex 0 1 2 3 4 5 6 8 9 a b c d e f bin 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 add r, m sub r, m addc r, m subc r, m and r, m xor r, m or r, m ret retsk rorc r stop s halt h nop ld r, m ske m, #n4 skne m, #n4 br addr add m, #n4 sub m, #n4 addc m, #n4 subc m, #n4 and m, #n4 xor m, #n4 or m, #n4 st m, r skge m, #n4 sklt m, #n4 call addr mov m, #n4 skt m, #n skf m, #n b 15 45 m pd17107(a1) 10.2 instructions legend asr : address stack register pointed to by the stack pointer addr : program memory address (11 bits, high-order two bits are always set to 0) cmp: compare flag cy : carry flag h : halt release condition m : data memory address specified by m r or m c m r : data memory row address (high order) m c : data memory column address (low order) n : bit position (4 bits) n4 : immediate data (4 bits) pc : program counter r : general register column address sp : stack pointer s : stop release condition ( ) : contents addressed by 46 m pd17107(a1 ) machine code op code operand operand operation instruction set mne- monic (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + cy (m) (m) + n4 + cy (r) (r) C (m) (m) (m) C n4 (r) (r) C (m) C cy (m) (m) C n4 C cy (r) (r) M (m) (m) (m) M n4 (r) (r) ? (m) (m) (m) ? n4 (r) (r) M (m) (m) (m) M n4 cmp 0, if (m) ? n = n, then skip cmp 0, if (m) ? n = 0, then skip (m) C n4, skip if zero (m) C n4, skip if not zero (m) C n4, skip if not borrow (m) C n4, skip if borrow cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 (r) (m) (m) (r) (m) n4 addr addr m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c m c 0111 m c m c m c r n4 r n4 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r r r n4 m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r m r 000 m r m r m r 00000 10000 00010 10010 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 00111 01000 11000 11101 r,m m,#n4 r,m m,#n4 r,m m,#n4 r,m m,#n4 r,m m,#n4 r,m m,#n4 r,m m,#n4 m,#n m,#n m,#n4 m,#n4 m,#n4 m,#n4 r r,m m,r m,#n4 add addc sub subc or and xor skt skf ske skne skge sklt rorc ld st mov add subtract logical operation test compare rotation transfer 01100 11100 00111 00111 00111 00111 00111 addr addr s h pc addr sp sp C 1, asr pc, pc addr pc asr, sp sp + 1 pc asr, sp sp + 1 and skip stop halt no operation 1110 1110 1111 1111 1111 0000 0000 s h 0000 000 001 010 011 100 br call ret retsk stop halt nop branch subroutine others 47 m pd17107(a1) 10.3 assembler (as17k) built-in macro instructions legend flag n : flg symbol < > : characters enclosed in < > can be omitted. built-in macro operation mnemonic operand n 1 n 4 1 n 4 1 n 4 1 n 4 1 n 4 1 n 4 flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n 48 m pd17107(a1 ) 11. electrical characteristics absolute maximum ratings (t a = 25 ?c) caution absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. be sure to use the product within the rated values. capacitance (t a = 25 ?c, v dd = 0 v) i/o: input/output c in c io input capacitance i/o capacitance parameter symbol conditions min. unit max. typ. f = 1 mhz 0 v for pins other than pins to be measured 15 15 pf pf rated value unit conditions parameter symbol C0.3 to +7.0 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to +11 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to +11 C5 C15 30 100 C40 to +110 C65 to +150 100 90 v v v v v v v ma ma ma ma c c mw supply voltage input voltage output voltage high-level output current low-level output current operating ambient temperature storage temperature allowable dissipation p0c, p0d, reset p0b p0c, p0d p0b each of p0c and p0d total of all pins each of p0b, p0c, and p0d total of all pins t a = 110 c 16-pin plastic dip 16-pin plastic sop v dd v i v o i oh i ol t a t stg p d when a built-in pull-up resistor is connected when a built-in pull-up resistor is not connected when a built-in pull-up resistor is connected when a built-in pull-up resistor is not connected 49 m pd17107(a1) dc characteristics (t a = -40 to +110 ?c, v dd = 2.5 to 6.0 v) notes 1. when a built-in pull-up resistor is connected 2. when a built-in pull-up resistor is not connected 3. this current excludes the current which flows through the built-in pull-up resistors. v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v oh1 v oh2 v ol1 v ol2 i lih1 i lih2 i lih3 i lil1 i lil2 i loh1 i loh2 i loh3 i lol r res r p0b i dd1 i dd2 i dd3 high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input leakage current low-level input leakage current high-level output leakage current low-level output leak- age current built-in pull-up resistor for pin reset built-in pull-up resistor for pin p0b power supply current note 3 parameter symbol conditions min. unit max. typ. p0c, p0d reset p0b note 1 note 2 p0c, p0d reset p0b p0c, p0d v dd = 4.5 to 6.0 v, i oh = C2 ma i oh = C200 m a, p0b, p0c, v dd = 4.5 to 6.0 v, p0d i ol = 15 ma i ol = 600 m a p0c, p0d, v in = v dd p0b, v in = v dd p0b, v in = 9 v note 2 p0c, p0d, v in = 0 v p0b, v in = 0 v p0c, p0d, v out = v dd p0b, v out = v dd p0b, v out = 9 v note 2 p0b, p0c, p0d, v out = 0 v 0.7v dd 0.8v dd 0.8v dd 0.8v dd 0 0 0 v dd C 2.0 v dd C 1.0 v dd v dd v dd 9 0.3v dd 0.2v dd 0.2v dd 2.0 0.5 5 5 10 C5 C5 5 5 10 C5 110 35 1.2 150 0.9 120 15 10 v v v v v v v v v v v m a m a m a m a m a m a m a m a m a k w k w ma m a ma m a m a m a 47 15 0.4 50 0.3 40 0.1 0.1 20 5 v dd = 5 v 10 %, f cc = 1.0 mhz 20 % v dd = 3 v 10 %, f cc = 250 khz 20 % v dd = 5 v 10 %, f cc = 1.0 mhz 20 % v dd = 3 v 10 %, f cc = 250 khz 20 % v dd = 5 v 10 % v dd = 3 v 10 % operation mode halt mode stop mode 50 m pd17107(a1 ) characteristics of data memory for holding data on low supply voltage in the stop mode (t a = C40 to +110 ?c) ac characteristics (t a = C40 to +110 ?c, v dd = 2.5 to 6.0 v) remark t cy = 8/f cc (f cc : frequency of the system clock oscillator) rls halt and rls stop input timing reset input timing v dddr i dddr data hold supply volt- age data hold supply current parameter symbol conditions min. unit max. typ. v dddr = 2.0 v 2.0 6.0 10 v m a 0.1 t cy t rlsh t rsl cpu clock cycle time (instruction execution time) high level width on rls halt and rls stop low level width on reset parameter symbol conditions min. unit max. typ. v dd = 4.5 to 6.0 v 6.1 21 10 10 180 180 m s m s m s m s rls halt , rls stop t rlsh t rsl reset 51 m pd17107(a1) system clock oscillator characteristics (t a = C40 to +110 ?c) caution the above conditions do not allow a resistance error. f cc system clock oscilla- tion frequency parameter symbol conditions min. typ. 700 170 120 1000 250 250 1300 330 380 khz khz khz max. unit v dd = 4.5 to 5.5 v, r osc = 24 k w v dd = 2.7 to 3.3 v, r osc = 100 k w v dd = 2.5 to 6.0 v, r osc = 100 k w 1000 500 100 50 110 100 500 v dd = 3.0 v resistor for oscillation r osc [k w ] clock oscillation frequency f cc [khz] f cc vs. r osc v dd = 5.0 v (t a = 25 ?c) 52 m pd17107(a1 ) 12. characteristic curves (reference) 0 12 3 4 5 6 0 100 200 300 400 500 600 700 800 900 1100 1000 r = 330 k w r = 100 k w r = 24 k w f cc vs. v dd (t a = 25 ?c) clock oscillation frequency f cc [khz] power supply voltage v dd [v] 1300 1000 500 380 300 100 50 45 30 10 5 3 1 0123456 clock oscillation frequency f cc [khz] power supply voltage v dd [v] osc 0 osc 1 r f cc vs. v dd for operation guarantee range (t a = C40 to +110 ?c) operation guarantee range 0 1234 5 6 500 330 100 50 24 10 1 operation guarantee range power supply voltage v dd [v] resistor for oscillation r osc [k w ] 0 osc 1 osc r r osc vs. v dd for operation guarantee range (t a = C40 to +110 ?c) -40 0 25 50 85 100 200 300 400 500 600 700 800 900 1100 1000 f cc vs. t a clock oscillation frequency f cc [khz] ambient temperature t a [?c] 110 v dd = 3.0 v, r = 100 k w v dd = 3.0 v, r = 330 k w v dd = 5.0 v, r = 24 k w 53 m pd17107(a1) caution the maximum absolute rating is C5 ma per pin. caution the maximum absolute rating is 30 ma per pin. osc 0 osc 1 r 0123456 1 10 50 100 500 1000 r = 24 k w operation r = 24 k w halt r = 100 k w operation r = 100 k w halt r = 330 k w operation r = 330 k w halt i dd vs. v dd (t a = 25?c) power supply current i dd [ a] power supply voltage v dd [v] m 35 30 25 20 15 10 5 0 01234 output low voltage v ol [v] output low current i ol [ma] i ol vs. v ol (t a = 25?c) v dd = 3.6 v v dd = 5 v v dd = 3 v v dd = 2.7 v v dd C v oh [v] C5 C4 C3 C2 C1 0 012 i oh vs. (v dd C v oh ) (t a = 25?c) output high current i oh [ma] v dd = 5 v v dd = 2.7 v v dd = 3.6 v v dd = 3 v 54 m pd17107(a1 ) 13. package drawings package drawings of mass-produced products (1/2) caution the es is different from the corresponding mass-produced products in shape and material. see "es package drawings (1/2)." 16 pin plastic dip (300 mil) item millimeters inches a b c f g h i j k 20.32 max. 2.54 (t.p.) 3.5?.3 0.51 min. 4.31 max. 1.27 max. l 0.25 7.62 (t.p.) 5.08 max. 6.5 n 1.1 min. p 0.800 max. 0.050 max. 0.043 min. 0.138?.012 0.020 min. 0.170 max. 0.200 max. 0.300 (t.p.) 0.256 0.01 0.043 min. 0.100 (t.p.) 1.1 min. p16c-100-300b-1 d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 r0 ~ 15 0~15 +0.004 ?.005 +0.004 ?.003 notes each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. item "k" to center of leads when formed parallel. 1) 2) m 18 16 9 a b i j g h c n f d m r k l p 55 m pd17107(a1) package drawings of mass-produced products (2/2) caution the es is different from the corresponding mass-produced products in shape and material. see "es package drawings (2/2)." 16 pin plastic sop (300 mil) item millimeters inches a b c e f g h i j 10.46 max. 1.27 (t.p.) 1.8 max. 1.55 7.7?.3 0.78 max. 0.12 1.1 5.6 m 0.1?.1 n 0.412 max. 0.031 max. 0.004?.004 0.071 max. 0.061 0.303?.012 0.220 0.043 0.005 0.050 (t.p.) p16gm-50-300b-4 p3 3 +7 note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.20 0.008 +0.10 ?.05 l 0.6?.2 0.024 0.10 ? +7 ? 0.004 +0.008 ?.009 +0.004 ?.002 +0.004 ?.003 a c d g p detail of lead end f e b h i l k m m 18 9 16 j n 56 m pd17107(a1 ) es package drawings (1/2) 16 1 20.32 1.91 0.33 2.54 17.78 7.62 0.254 0.89 16 pin plastic sop (300 mil) (unit: mm) 57 m pd17107(a1) es package drawings (2/2) 16 pin ceramic sop (for es) item millimeters inches a b c d e f g h i j 10.16 1.27 (t.p.) 2.54 max. 1.7 12.1 1.02 max. k t 0.025 min. 4.8 2.35 6.9 0.13 u 0.43 0.48 max. 0.40 0.041 max. 0.017 0.019 max. 0.10 max. 0.067 0.476 0.272 0.093 0.005 0.189 0.0 min. 0.05 (t.p.) x16b-50b-1 t uk a b 16 9 18 c d j i h f g e 58 m pd17107(a1 ) 14. recommended soldering conditions the conditions listed below shall be met when soldering the m pd17107(a1). for details of the recommended soldering conditions, refer to our document smd surface mount technology manual (iei-1207). please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 14-1 soldering conditions for surface-mount devices m pd17107gs(a1)- : 16-pin plastic sop (300 mil) caution do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). table 14-2 soldering conditions for through hole mount devices m pd17107cx(a1)- : 16-pin plastic dip (300 mil) caution in wave soldering, apply solder only to the terminal section. care must be taken that jet solder does not come in contact with the main body of the package. recommended conditions soldering process soldering conditions infrared ray reflow vps partial heating method ir35-00-2 vp15-00-2 C peak package's surface temperature: 235 ?c reflow time: 30 seconds or less (210 ?c or more) maximum allowable number of reflow processes: 2 59 m pd17107(a1) appendix development tools the following support tools are available for developing programs for the m pd17107(a1). hardware name description the ie-17k, ie-17k-et, and emu-17k are in-circuit emulators applicable to the 17k series. the ie-17k and ie-17k-et are connected to the pc-9800 series (host machine) or ibm pc/ at tm through the rs-232-c interface. the emu-17k is inserted into the extension slot of the pc-9800 series (host machine). use the system evaluation board (se board) corresponding to each product together with one of these in-circuit emulators. simplehost ? , a man machine interface, implements an advanced debug environment. the emu-17k also enables user to check the contents of the data memory in real time. the se-17107 is an se board for the m pd17107, m pd17107l, or m pd17p107. it is used solely for evaluating the system. it is also used for debugging in combination with the in- circuit emulator. the ep-17103cx is an emulation probe for the m pd17103, m pd17103l, m pd17p103, m pd17107, m pd17107l, or m pd17p107. the af-9703, af-9704, af-9705, and af-9706 are prom writers for the m pd17p107. use one of these prom writers with the program adapter, af-9799, to program the m pd17p107. the af-9799 is a socket unit for the m pd17p103, m pd17p104, m pd17p107, and m pd17p108. it is used with the af-9703, af-9704, af-9705, or af-9706. in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 se board (se-17107) emulation probe (ep-17103cx) prom programmer af-9703 note 3 af-9704 note 3 af-9705 note 3 af-9706 note 3 programmer adapter (af-9799 note 3 ) notes 1. low-end model, operating on an external power supply 2. the emu-17k is a product of ic co., ltd. contact ic co., ltd. (tokyo, 03-3447-3793) for details. 3. the af-9703, af-9704, af-9705, af-9706, and af-9799 are products of ando electric co., ltd. contact ando electric co., ltd. (tokyo, 03-3733-1151) for details. 60 m pd17107(a1 ) 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc 5.25-inch, 2hd 3.5-inch, 2hd 5.25-inch, 2hc 3.5-inch, 2hc os part number description name software m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17103 note m s5a13as17103 note m s7b10as17103 note m s7b13as17103 note m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k note m s as17103 contains a device file for the m pd17103, m pd17104, m pd17107, m pd17108, m pd17103l, m pd17104l, m pd17107l, or m pd17108l. remark the following table lists the versions of the operating systems described in the above table. note ms-dos versions 5.00 and 5.00a and pc dos ver. 5.0 are provided with a task swap function. this function, however, cannot be used in these software packages. distribution media host machine pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at ms-dos tm pc dos tm ms-dos pc dos as17k is an assembler applicable to the 17k series. in developing m pd17107(a1) programs, as17k is used in combination with a device file (as17103). as17103 contains a device file for the m pd17107(a1) and m pd17p107. it is used together with the assembler (as17k) which is applicable to the 17k series. simplehost , running on the windows tm , provides man- machine-interface in developing programs by using a personal computer and the in-circuit emulator. 17k series assembler (as17k) device file (as17103) support software ( simplehost ) ms-dos pc dos windows ms-dos pc dos windows ver. 3.30 to ver. 5.00a note ver. 3.1 to ver. 5.0 note ver. 3.0 to ver. 3.1 os versions 61 m pd17107(a1) cautions on cmos devices 1 countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. 2 cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate- level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. 3 statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first. m pd17107(a1) simplehost is a registered trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 |
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